RAME: A Supervisory System Enforcing Design for Safety and Mission Success
RAME focuses on the concepts and designs for
validation of design integrity of IP-based ASICs, mixed-signal ASICs,
and system-on-a-chip. Our motivation is to transform
design-for-safety (DFS) practice from a traditional ad-hoc process
that relies on error-prone, textual-document manipulation to
a stringent engineering process that ensures DFS to keep up with
the rapidly growing complexity of avionics systems.
In particular, RAME is to be built upon an information
infrastructure that maintains the fault models, knowledge base,
and failure reporting/tracking system.
The application of model- and knowledge-based techniques
leads our approach differs significantly from the prior
approaches to failure analysis in the following respects:
- Goal:
-
Unlike traditional FMEA approaches,
our goal is not only to ease the analysis process and to enable
timely feedbacks, but also to ensure the integrity of the process
and results. In particular, the automated FMECA in RAME will
prevent an analysis from missing failure modes, mis-identifying
causes or effects, or suggesting inappropriate detection
methods.
- Extent of automation:
-
Unlike existing failure analysis tools
which are responsible to help an engineer to initiate a partial
failure analysis worksheet that needs to be further processed
(i.e., to fill in the blanks) manually by the engineer,
our FMECA automation engine will responsible for the whole process
and supply a completed worksheet that provides all the analysis
results.
- Means of automation:
-
Most automation tools for failure mode analysis were implemented
to emulate the manual process of failure analysis.
Differing from those ``cookbook-based'' approaches,
we use a semi-formal approach to the automation by utilizing
the VHDL design source code, fault models, and
knowledge-based techniques.
